1. Field of the Invention
The present invention relates a clock signal reproduction device and a clock signal reproduction method, and more particularly relates to a clock signal reproduction device and a clock signal reproduction method for reproducing a clock signal used for demodulating a modulated wave.
2. Description of the Related Art
In transmitting information using digital data, a clock signal generated by an oscillator or the like is generally used. Specifically, for transmitting information digital data is generated with such a method of representing the objective information to be transmitted, by a value of digital data at a predetermined timing specified with reference to the clock signal. Then, the generated digital data is modulated and transmitted.
Accordingly, in order to receive the digital data and reproduce (re-generate) the information, a receiver needs to acquire the same clock signal as used for generating the digital data.
Incidentally, in wireless communication, a radio wave sent out from a transmitting device reaches an antenna of a receiving device as a mixture of a direct wave and a plurality of reflected waves which are combined in the transmission path. Therefore, a plurality of modulated waves that have different phases and amplitudes are input to the receiving device. Under the influence of such a phenomenon of a radio wave traveling through many paths other than the path of the direct wave thereby incurring intense fluctuations in the phase and amplitude (i.e., a multi-path fading), the clock signal reproduced by the receiving device might cause a clock slip in the worst case.
Hence, various methods have conventionally been proposed, for enabling the device for receiving digital data to accurately reproduce the clock signal used for reproducing the received digital data.
For example, according to a method disclosed in Unexamined Japanese Patent Application KOKAI Publication No. S58-95447, a receiving device reproduces the clock signal by calculating the exclusive OR of the demodulated signal and a signal obtained by delaying the demodulated signal by a half time slot, and inputs the reproduced clock signal to a PLL (Phase Locked Loop) circuit as an originally oscillated input signal to control the phase of the clock signal.
According to a method disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2003-258783, because a slip (phase difference) that amounts to one or more clocks cannot be corrected only by controlling the phase of the clock signal with the use of a PLL circuit, a receiving device continuously monitors the clock signal reproduced from the demodulated signal and a clock signal obtained from a VCO (Voltage Controlled Oscillator) in the PLL circuit, and detects a slip that amounts to one or more clocks and that is produced between the two clock signals, and corrects the VCO with use of the detection result.
Further, according to a method disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H9-275396, a receiving device solves the problem of the phase of the clock signal reproduced by itself going out of control due to an error signal produced inside a PLL circuit in a case where the clock signal as reproduced has lost any pulse that should constitute the clock signal. Specifically, according to this method, when the clock signal reproduced by the receiving device from the demodulated signal becomes asynchronous with a clock signal obtained from a VCO in the PLL circuit, the receiving device restricts an increase of the value of the error signal by narrowing the width of the high-level side or the low-level side of the pulses oscillated by the VCO depending on which of the high-level side and the low-level side of the pulses constituting the reproduced clock signal has been lost.
In order to correct the VCO by employing the method disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2003-258783, the receiving device needs to continuously monitor a slip that amounts to one clock or more and that is produced between the clock signal reproduced by the receiving device and the clock signal from the VCO. And the monitoring period generally lasts for several ten clocks. Thus, according to the method of Unexamined Japanese Patent Application KOKAI Publication No. 2003-258783, it is often impossible to accurately reproduce the clock signal, because the phase of the clock signal cannot be corrected quickly.
Further, the method disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H9-275396 is a method for changing the pulse width of the reproduced clock signal, but not a method for correcting the phase of the clock signal.